Power-Aware Memory Allocation for Embedded Data-Intensive Signal Processing Applications

Many signal processing systems, particularly in the multimedia and telecommunication domains, are synthesized to execute data-intensive applications: their cost related aspects ­ namely power consumption and chip area ­ are heavily influenced, if not dominated, by the data access and storage aspects. This chapter presents a power-aware memory allocation methodology. Starting from the high-level behavioral specification of a given application, this framework performs the assignment of of the multidimensional signals to the memory layers ­ the on-chip scratch-pad memory and the off-chip main memory ­ the goal being the reduction of the dynamic energy consumption in the memory subsystem. Based on the assignment results, the framework subsequently performs the mapping of signals into the memory layers such that the overall amount of data storage be reduced. This software system yields a complete allocation solution: the exact storage amount on each memory layer, the mapping functions that determine the exact locations for any array element (scalar signal) in the specification, and, in addition, an estimation of the dynamic energy consumption in the memory subsystem

Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations

The storage requirements of the array-dominated and looporganized algorithmic specifications running on embedded systems can be significant. Employing a data memory space much larger than needed has negative consequences on the energy consumption, latency, and chip area. Finding an optimized storage of the usually large arrays from these algorithmic specifications is an important step during memory allocation. This paper proposes an efficient algorithm for mapping multi-dimensional arrays to the data memory. Similarly to [13], it computes bounding windows for live elements in the index space of arrays, but this algorithm is several times faster. Moreover, since this algorithm works not only for entire arrays, but also parts of arrays – like, for instance, array references or, more general, sets of array elements represented by lattices [11], this signal-to-memory mapping technique can be also applied in multi-layer memory hierarchies

COMPUTATION OF THE MINIMUM DATA STORAGE FOR MULTI-DIMENSIONAL SIGNAL PROCESSING

The amount of the data storage in signal processing systems, whose behavior is described by loop-organized algorithmic specifications, has an important impact on the overall energy consumption, chip area, as well as system performance. This paper presents a non-scalar approach for computing the minimum storage requirements in high-level procedural specifications, where the main data structures are multi-dimensional arrays. This methodology uses both algebraic techniques specific to the data-flow analysis used in modern compilers and, also, more recent advances in the theory of polyhedra. In contrast with all the previous works which are only estimation methods, this approach can perform the exact computation of the minimum data storage even for applications with numerous loop nests and complex array references

EFFICIENT ASSIGNMENT ALGORITHM FOR MAPPING MULTIDIMENSIONAL SIGNALS INTO THE PHYSICAL MEMORY

The storage requirements in data-intensive multidimensional signal processing systems have a significant impact on the system performance as well as on essential design parameters, like the overall power consumption and chip area. This paper addresses the problem of efficiently mapping the multidimensional signals from the algorithmic specification of the system into the physical memory. Different from all the previous mapping models that aim to optimize the memory sharing between the elements of a same array, this proposed assignment algorithm takes also into account the possibility of memory sharing between different arrays. As a consequence, the experiments with this novel signal-to-memory mapping approach exhibit important savings of data storage resulted after mapping